The present application relates to three dimensional (3D) vertical integration of semiconductor devices, and more particularly to a bonding method for forming 3D stacked assemblies and a vacuum distribution plate that can be used in such a bonding method.
One type of 3D integrated circuit can include two or more layers of active electronic components stacked vertically and electrically joined with through-substrate vias and solder bumps. The 3D stacked assemblies can provide numerous benefits such as increased package density yielding smaller interconnect footprints between the semiconductor devices, and improved bandwidth due to the short connection lengths made possible by the use of through-substrate vias. The 3D stacked assemblies described above may be fabricated in any number of known methods. Some 3D stacked assemblies can include one or more silicon interposers which can be used to re-direct circuitry between a chip carrier and one or more top chips.
Warping of the components of the 3D integrated semiconductor devices during typical assembly processes can result in failed solder bump connections and short circuits. The influence warping has on 3D chip packaging can become more significant as the chip size increases and the component thickness decreases.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.